University of Illinois Urbana-Champaign

ESD robustness of stacked NMOS transistors for high-voltage tolerant output drivers in FinFET technology

Guo, Yuanqi

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https://hdl.handle.net/2142/129479

Description

Title
ESD robustness of stacked NMOS transistors for high-voltage tolerant output drivers in FinFET technology
Author(s)
Guo, Yuanqi
Issue Date
2025-01-13
Director of Research (if dissertation) or Advisor (if thesis)
Rosenbaum, Elyse
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
  • ESD
  • Stacked NMOS
  • high-voltage tolerant output drivers
  • CDM
  • VF-TLP
Abstract
This thesis describes a study designed to enhance the understanding of the reliability of doubly-stacked NMOS transistors under Charged Device Model (CDM) electrostatic discharge (ESD) conditions. Stacked NMOS are commonly used in high-voltage tolerant output drivers. The transistors used for this study are fabricated in a FinFET CMOS process. The test structures were designed such that the robustness of doubly-stacked NMOS devices could be evaluated as a function of the applied gate bias and the layout style. Very-Fast Transmission Line Pulse (VF TLP) measurements were used to evaluate the ESD robustness and the dynamic response. Based on the experimental results and subsequent analysis, design recommendations and a biasing strategy for cascoded output drivers are proposed. The objective is to improve the ESD reliability of high-voltage tolerant output drivers.
Graduation Semester
2025-05
Type of Resource
Thesis
Handle URL
https://hdl.handle.net/2142/129479
Copyright and License Information
Copyright 2025 Yuanqi Guo

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