Process-induced strain engineering in two dimensional semiconductors

Zhang, Yue

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https://hdl.handle.net/2142/129499 Copy

Description

Title

Process-induced strain engineering in two dimensional semiconductors

Author(s)

Zhang, Yue

Issue Date

2025-03-07

Director of Research (if dissertation) or Advisor (if thesis)

van der Zande, Arend

Doctoral Committee Chair(s)

van der Zande, Arend

Committee Member(s)

• Johnson, Harley
• Huang, Pinshane
• Ertekin, Elif

Department of Study

Mechanical Sci & Engineering

Discipline

Mechanical Engineering

Degree Granting Institution

University of Illinois Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

• 2D Semiconductors
• Strain engineering

Abstract

Atomically thin, two-dimensional (2D) electronic materials such as transition metal dichalcogenides (TMDs) represent the ultimate thickness limit in scaling down integrated circuits. This paradigm shift facilitates the heterogeneous integration of 2D electronic devices into the current silicon-based CMOS technology library. A key challenge is understanding CMOS process compatibility with 2D materials, and what new fabrication capabilities are enabled by applying common CMOS processes on 2D devices. In particular, there is a knowledge gap in how thin film stress, commonly found across thin film deposition processes, interacts with 2D few-layers and how the van der Waals interface affects strain transfer during CMOS processes. In this dissertation, we show that CMOS process-induced stress applies a controllable strain when evaporating thin films on 2D monolayers and heterobilayers. We use thin film evaporation as an example, and selectively deposit lithographically-patterned thin film magnesium oxide (MgO), known as stressors, onto 2D monolayers and heterobilayers with e-beam evaporation. By tracking the changes in Raman signature modes in monolayer MoS₂ and WSe₂, we qualitatively estimate the strain, and the result is independently verified with the photoluminescence emission peak mode. Importantly, engineering the mechanical boundary condition enables the application of complex, spatially heterogeneous strain and strain gradients that are designable. This new ability has two impacts. In the monolayer, we demonstrate inducing up to 0.8% complex strain distribution that is challenging for polymer-based strain engineering methods. In the artificially stacked MoS₂/WS₂ heterobilayer, for the top layer, the MgO stressor applies a uniform, ~1% strain while the bottom layer is unaffected, creating layer-dependent strain, or heterostrain. The patterned stressor strategy allows direct device integration for strained 2D materials. As a demonstration, we start with a monolayer MoS₂ transistor, and repeatedly deposit the MgO stressor while measuring the carrier transport at different stressor thicknesses. While the stressor is below the critical thickness (~150 nm), the device conductivity linearly improves due to the enhancement of electron carrier mobility: at ~0.4% strain, we observe over 60% electron mobility enhancement. Compared to similar studies with polymer-based strain engineering methods, our strategy has a similar enhancement strength, while manifesting the integration of highly strained 2D systems into other solid devices. Finally, we show that the patterned stressor helps access polarizations in the 2D valleytronics. Specifically, 2D TMDs such as MoS₂ and WSe₂ host rich valley physics but do not allow valley polarizations due to lattice symmetry. We show that the patterned stressor effectively engineers the material inversion and rotational symmetry and yields robust valley polarization. Since valley polarization is determined by the lattice symmetry, the polarization must be sensitive to the directionality of strain and strain gradient. We use the patterned stressor to systematically test the valley polarization dependence on strain directionality and show that the valley polarization turns on and off at different directions of strain gradient, forming a two-fold rotational symmetry. Our results provide a practical route to generate strong, robust, and localized valley polarizations, a prerequisite for all practical valleytronic devices. Therefore, the stressor technique is well suited for further explorations in 2D valleytronics, such as valley carrier transport, trapping, and decoherence. Overall, engineering process-induced stress provides opportunities to fine-tune the electronic properties of 2D materials with strain, and directly incorporate strained 2D systems into the current CMOS architecture. More broadly, highly localized strain and strain gradients enable unprecedented quantum functional devices made of 2D monolayers and heterostructures. Deterministically designing and applying strain with thin film stressors accelerates the integration of diverse strain-enabled multifunctional 2D devices into CMOS circuits, defined as "more than Moore" in technology roadmaps.

Graduation Semester

2025-05

Type of Resource

Thesis

Handle URL

https://hdl.handle.net/2142/129499

Copyright and License Information

Copyright 2025 Yue Zhang

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