Scalable High-Level Synthesis for AI accelerator design

Ye, Hanchen

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https://hdl.handle.net/2142/129760 Copy

Description

Title

Scalable High-Level Synthesis for AI accelerator design

Author(s)

Ye, Hanchen

Issue Date

2025-05-01

Director of Research (if dissertation) or Advisor (if thesis)

Chen, Deming

Doctoral Committee Chair(s)

Chen, Deming

Committee Member(s)

• Adve, Vikram
• Huang, Jian
• Neuendorffer, Stephen

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

• High-Level Synthesis (HLS)
• AI Accelerator
• FPGA
• ASIC
• Design Space Exploration (DSE)
• Deep Neural Networks (DNNs)
• Compiler
• Dataflow
• Intermediate Representation (IR)
• MLIR
• Electronic Design Automation (EDA)
• Hardware-Software Co-design
• Large Language Models (LLMs)
• Convolutional Neural Networks (CNNs)

Abstract

The growing scale and complexity of deep neural networks (DNNs) present significant challenges for efficient hardware acceleration. High-Level Synthesis (HLS) has emerged as a promising methodology to enhance design productivity for FPGA- and ASIC-based accelerators. However, existing HLS workflows struggle to scale effectively due to their inability to address cross-stack co-design challenges spanning architecture design, compiler infrastructure, and Electronic Design Automation (EDA) algorithms. This dissertation proposes a comprehensive and scalable HLS methodology for AI accelerator design by innovating across three synergistic levels. At the design level, we present HybridDNN and DNNExplorer, two frameworks that facilitate the generation and exploration of hardware accelerators through algorithm-aware modeling and fine-grained design space exploration. At the compiler level, we develop ScaleHLS, HIDA, and StreamTensor, which together form a scalable HLS compiler stack that supports multi-level intermediate representations, design space optimizations, and hardware-aware scheduling for both generic and dataflow-based accelerators. At the EDA level, we introduce ISDC, an iterative scheduling algorithm that integrates feedback from downstream tools to significantly enhance resource utilization. Collectively, these contributions constitute a full-stack solution to scalable HLS, advancing the productivity, performance, and adaptability of AI accelerator design.

Graduation Semester

2025-05

Type of Resource

Thesis

Handle URL

https://hdl.handle.net/2142/129760

Copyright and License Information

Copyright 2025 Hanchen Ye

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