Enhancing system-level efficiency using SNICs

Vanavasam, Srikar

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https://hdl.handle.net/2142/129936 Copy

Description

Title

Enhancing system-level efficiency using SNICs

Author(s)

Vanavasam, Srikar

Issue Date

2025-07-13

Director of Research (if dissertation) or Advisor (if thesis)

Kim, Nam Sung

Department of Study

Siebel School Comp & Data Sci

Discipline

Computer Science

Degree Granting Institution

University of Illinois Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• Computer Architecture
• Network
• Datacenter

Abstract

The rapid increase in network bandwidth continues to outpace the scaling of single-thread CPU performance, creating a significant "datacenter tax" where host CPUs are consumed by infrastructure tasks. To address this, modern servers employ a variety of specialized hardware, including on-chip accelerators and programmable Smart Network Interface Cards (SNICs). This thesis provides a multi-faceted architectural analysis of these components, focusing on performance trade-offs, next-generation interconnects, and novel offload frameworks. First, a characterization of a modern host CPU (Intel Sapphire Rapids) versus an integrated SNIC processor (NVIDIA BlueField-3) reveals the fundamental performance and energy trade-offs of executing network functions, establishing that the optimal processing location is heavily dependent on workload intensity. Second, the host interconnect is addressed by characterizing the performance of offloading kernel subsystems (\texttt{zswap} and \texttt{ksm}) over the new Compute Express Link (CXL) protocol versus traditional PCIe. The results quantify the latency advantages of CXL for fine-grained, latency-sensitive host-accelerator communication. Third, a novel framework, AccDirect, is presented. It leverages an SNIC to orchestrate PCIe Peer-to-Peer (P2P) communication with an on-chip accelerator, the Intel Dynamic Load Balancer (DLB). An end-to-end comparison demonstrates that this approach significantly reduces system power and improves application throughput compared to traditional software-based load balancers by eliminating the host CPU from the data path. Finally, a deep-dive characterization of a novel programmable engine on a state-of-the-art SNIC, the NVIDIA BlueField-3 Data Path Accelerator (DPA), reveals its architectural properties and performance bottlenecks, highlighting the profound impact of its memory subsystem on overall performance. Collectively, these studies provide critical insights for architects and practitioners seeking to build and optimize efficient, next-generation data center systems.

Graduation Semester

2025-08

Type of Resource

Thesis

Handle URL

https://hdl.handle.net/2142/129936

Copyright and License Information

Copyright 2025 Srikar Vanavasam

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