University of Illinois Urbana-Champaign

Investigation of factors determining charged device model electrostatic discharge reliability of integrated circuits

Drallmeier, Matthew

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https://hdl.handle.net/2142/130032

Description

Title
Investigation of factors determining charged device model electrostatic discharge reliability of integrated circuits
Author(s)
Drallmeier, Matthew
Issue Date
2025-07-11
Director of Research (if dissertation) or Advisor (if thesis)
Rosenbaum, Elyse
Doctoral Committee Chair(s)
Rosenbaum, Elyse
Committee Member(s)
  • Schutt-Aine, Jose E
  • Bernhard, Jennifer T
  • Chen, Xu
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
  • Electrostatic Discharge (ESD)
  • Charged Device Model (CDM)
  • Integrated Circuit Reliability
  • Gate Oxide Breakdown
Abstract
Electrostatic discharge (ESD) protection is required at the high-speed input/output (IO) interfaces of integrated circuits (ICs) to ensure reliability, but it adds loading capacitance that hinders performance; effective ESD designs must balance that tradeoff. A critical aspect of effective ESD design is a comprehensive understanding of the voltage and current waveforms inside an IC during an ESD event and the voltage or current level at which the devices inside the circuit will be damaged. This dissertation presents two measurement methodologies that advance our knowledge of those factors, which in turn, enhance designers’ ability to develop optimal ESD protection. The first methodology is an on chip pulse generator which can apply clean, square pulses with pulse width down to 100 ps to an integrated victim device. The on chip pulse generator is used to characterize gate dielectric breakdown on the sub ns timescale. The second methodology is an on chip probe that can read out the on chip voltage waveforms during an ESD test in real time. The probe is used to capture transient voltage waveforms at internal nodes of high speed IO circuits located in a packaged IC, providing valuable insights into their ESD reliability.
Graduation Semester
2025-08
Type of Resource
Thesis
Handle URL
https://hdl.handle.net/2142/130032
Copyright and License Information
Copyright 2025 Matthew Drallmeier

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