Reduced Complexity Encoding of Non-binary Quasi-Cyclic Low-Density Parity-Check Codes

Bharadwaj, Karthik; Venkataramanappa, Suresh Kumar; Kumar, Pavan; Mishra, Deepak; Garani, Shayan Srinivasa

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https://hdl.handle.net/2142/130282 Copy

Description

Title

Reduced Complexity Encoding of Non-binary Quasi-Cyclic Low-Density Parity-Check Codes

Author(s)

• Bharadwaj, Karthik
• Venkataramanappa, Suresh Kumar
• Kumar, Pavan
• Mishra, Deepak
• Garani, Shayan Srinivasa

Issue Date

2025-09-17

Keyword(s)

• Quasi-cyclic
• Non-binary
• LDPC
• Encoding
• Decoding
• Codec

Abstract

Non-binary low-density parity-check (LDPC) codes offer enhanced coding performance, particularly for small and medium block lengths. We develop encoders for non-binary quasi-cyclic (QC) LDPC codes. A full-rank parity-check matrix is used to construct a generator matrix with a block-circulant structure, thereby reducing the encoder’s computational complexity, suitable for resource-constrained applications. The proposed structured code designs demonstrate substantially reduced complexity in the encoding and decoding processes, while maintaining decoder performance within 0.2 dB of signal-to-noise ratio (SNR) compared to random assignment of optimal nonzero Galois field (GF) entries in the parity-check matrix. Last, we validate the design architecture by implementing the encoder for a (2, 4)-regular 1/2 -rate (64, 32) non-binary QC LDPC code over GF(256) with a throughput of 1.6 Gbps on an FPGA board using a two-thread architecture.

Publisher

Allerton Conference on Communication, Control, and Computing

Series/Report Name or Number

2025 61st Allerton Conference on Communication, Control, and Computing Proceedings

ISSN

2836-4503

Type of Resource

Text

Genre of Resource

Conference Paper/Presentation

Language

eng

Handle URL

https://hdl.handle.net/2142/130282&&

Copyright and License Information

Copyright 2025 owned by the authors.

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