Victim structures for predicting the ESD reliability of IO circuits
Sear, Patrick
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https://hdl.handle.net/2142/132461
Description
Title
Victim structures for predicting the ESD reliability of IO circuits
Author(s)
Sear, Patrick
Issue Date
2025-09-22
Director of Research (if dissertation) or Advisor (if thesis)
Rosenbaum, Elyse
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
ESD
Circuit Design
Abstract
Compact, wafer-level ESD victim circuits that fail similarly to real IO circuits are used to validate the performance of ESD protection schemes in a 65-nm process technology. Electrical failure analysis identifies the device that fails during the ESD testing. Effects of circuit topologies and victim design choices on measured failure level are evaluated, and a follow-up chip is designed to extend the testing capability to CDM. The measured response of victim circuits is utilized to validate ESD compact models. Compact models are used to investigate the prediction of device failure in simulation.
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