A 1.7GS/s SAR ADC in 28nm CMOS

Burns, John Erick

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https://hdl.handle.net/2142/132607 Copy

Description

Title

A 1.7GS/s SAR ADC in 28nm CMOS

Author(s)

Burns, John Erick

Issue Date

2025-12-12

Director of Research (if dissertation) or Advisor (if thesis)

Hanumolu, Pavan K

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• SAR ADC
• Pipelined SAR ADC
• Passive residue transfer
• Partial interleaving

Abstract

This thesis presents a 1.7GS/s 9b single channel SAR ADC in 28nm CMOS technology. The main focus of the thesis is the leveraging of the pipelining, passive residue transfer, and partial interleaving techniques to increase sample rate of the ADC. The first chapter explains the motivation for increasing the single channel ADC speed as well as the operation of the SAR ADC and pipelined SAR ADC and their inherent limitations. The second chapter presents the architecture investigated in this project. The third chapter details the circuit level implementation of the ADC. The fourth chapter shows simulation results, and the fifth chapter presents the conclusions.

Graduation Semester

2025-12

Type of Resource

Thesis

Handle URL

https://hdl.handle.net/2142/132607

Copyright and License Information

Copyright 2025 John Burns

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