Systems and circuits for broadband contactless and wireline transceivers

Younis, Mohamed Badr

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https://hdl.handle.net/2142/132773 Copy

Description

Title

Systems and circuits for broadband contactless and wireline transceivers

Author(s)

Younis, Mohamed Badr

Issue Date

2025-11-24

Director of Research (if dissertation) or Advisor (if thesis)

Hanumolu, Pavan K

Doctoral Committee Chair(s)

Hanumolu, Pavan K

Committee Member(s)

• Shanbhag, Naresh R
• Rosenbaum, Elyse
• Schutt-Aine, Jose E

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

• clock and data recovery (CDR)
• capacitive coupling
• air gap link
• transceiver (TRX)
• transmitter (TX)
• receiver (RX)
• modulo-2 sampling
• Tomlinson-Harashima
• precoding
• phase locked loop (PLL)
• clock generator, sub-sampling
• least mean square (LMS)
• calibration
• adaptation
• quadrupler
• multiplier
• deterministic jitter

Abstract

Recent years have witnessed significant growth in global data traffic, primarily driven by the exponential increase in both the number of users and the amount of data processed by various applications. This has motivated the development of cost- and energy-efficient high-speed interconnects capable of managing the significant bandwidth demands of such applications. The most effective solution for transferring these large volumes of data is broadband wireline communication systems. They cover a wide range of applications across all scales, from supercomputing devices in data centers to mobile consumer devices. Advancements in circuit design and technology scaling have enabled the development of efficient wireline transceivers. However, their communication bandwidth still struggles to keep pace with the rapid increase in data traffic, making wireline communication the bottleneck in overall system performance. Additionally, in user applications such as laptops, displays, and smartphones, these systems typically employ physical connectors as the communication channel. These types of connections are susceptible to mechanical damage and affect the overall system reliability. In this dissertation, techniques at both the system and circuit levels are proposed to improve the reliability and performance of broadband communication systems. In the first contribution, a contactless capacitively-coupled transceiver is presented to replace mechanical connectors in applications where a communication link can be established over a few millimeters of gap distance. It incorporates a 1-D partial response channel and a Tomlinson-Harashima precoding scheme in the transmitter to enable feedforward data recovery in the receiver. A novel dual-edge-tracking clock and data recovery loop (DE-CDR) is introduced to retrieve the clock from the received 3-level data stream featuring a fast phase-locking loop (PLL) and a slow delay-locking loop (DLL). The transceiver operates at a DisplayPort rate of 5.2 Gb/s and achieves an error-free operation over a 3 mm air-gap. It is fabricated in a 65 nm CMOS process and operates at a 1 V power supply with 4.7 pJ/b energy efficiency. The second contribution proposes a wideband ring-oscillator-based clock generator as an approach for per-lane clock multiplication in dense multi-lane high-speed SerDes. To avoid the challenges associated with directly synthesizing a high frequency clock using a phase-locked loop (PLL), the clock generator is built by a cascade of a ring-oscillator-based PLL and an open loop quadrupler. A sub-sampling error extraction (SSEE) technique is introduced to fully detect the deterministic jitter (DJ) in the output clock at much lower speeds with minimal power overhead. An orthogonal 3-path LMS-based adaptation algorithm is implemented to suppress the DJ using 5 fs-resolution digital to time converters (DTCs) at the quadrupler input. Fabricated in a 16-nm FinFET process, the proposed clock generator produces an output clock from 12 - 25 GHz while maintaining a worst-case spur below -50 dBc across the whole band. At 25 GHz, the clock generator achieves a total integrated random jitter (10 KHz - 100 MHz) of 97.9 fsrms while consuming a total power of 39.8 mW from 0.8 V supply, with the quadrupler contributing only 22 fsrms of additive jitter.

Graduation Semester

2025-12

Type of Resource

Thesis

Handle URL

https://hdl.handle.net/2142/132773

Copyright and License Information

Copyright 2025 Mohamed Badr Younis

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