This thesis presents the design of a high-speed Gm-R residue amplifier used in a pipelined-SAR ADC, implemented in a 28nm CMOS process. The proposed design achieves good linearity and low gain variation due to temperature using a constant-gm biasing network. The thesis is organized as follows: Chapter 1 introduces the concepts of ADCs and residue amplification. Chapter 2 discusses the backgrounds on architecture of the SAR ADC and pipelined-SAR ADC, and introduces residue amplifier design for pipelined-SAR ADC. Chapter 3 introduces the ADC architecture that is used with the Gm-R residue amplifier, design process and considerations of the Gm-R residue amplifier and layout. Chapter 4 shows the simulation results for the residue amplifier gain and nonlinearity, along with the ADC system level performances. Chapter 5 summarizes the findings and concludes the thesis.
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