Development of electrical and optical devices for next generation high-speed optical interconnects
Liu, Zetai
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Permalink
https://hdl.handle.net/2142/132812
Description
Title
Development of electrical and optical devices for next generation high-speed optical interconnects
Author(s)
Liu, Zetai
Issue Date
2025-12-10
Director of Research (if dissertation) or Advisor (if thesis)
Feng, Milton
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
High Speed Data Com, VCSEL, HBT, Fabrication, Testing
Language
eng
Abstract
Rapid advances in AI, LLMs, and IoT are pushing data traffic toward >1.6 Tb/s optical links with much lower energy per bit. VCSEL based multichannel transceivers are one of the most cost- and power-efficient choice for short-reach interconnects, but further scaling is limited by modal dispersion in multimode VCSELs and bandwidth/power ceilings in both VCSELs and silicon driver/control ICs as per-lane rates exceed 200 Gb/s. Accordingly, overcoming optical limitations requires both aggressive aperture scale-down and targeted process advancements in VCSEL fabrication. The electrical limits motivate using higher-speed electronic devices such as InP based Type-II DHBTs. Meanwhile, cryogenic and quantum computing demand ultra-efficient links bridging cryogenic processors to room-temperature peripheral electronics; Cryo-VCSELs offer ~100 GHz bandwidth at few milliampere bias range and enable >448-Gb/s PAM-4 operation but require tighter process control and microcavity-scaling insight.
This thesis advances two fronts: first, a wafer-scale, OpenCV-based automated oxide-aperture measurement method that replaces manual ImageJ, enabling full-wafer oxidation maps at high throughput and exposing critical nonuniformities for <3-µm apertures; and, second, a quantitative study of emitter-ledge effects in sub-micron InP/GaAsSb Type-II DHBTs, showing a 160-nm ledge can more than double DC current gain β by suppressing surface recombination, but with trade-offs in ideality factor, yield, base resistance, and fT/fmax.
Together, these results provide the process capability and device understanding needed to co-optimize Cryo-VCSEL sources and InP-DHBT electronics for fJ/bit-class, long-reach optical interconnects in hybrid-temperature computing systems.
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