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https://hdl.handle.net/2142/132815
Description
Title
A high resolution programmable thermal test chip
Author(s)
Wu, Zaizhou
Issue Date
2025-12-11
Director of Research (if dissertation) or Advisor (if thesis)
Kumar, Rakesh
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
thermal test chip
Abstract
As silicon technology continues to scale, power densities in integrated circuits are rising, driving the need for more accurate and fine-grained thermal characterization methods. While numerical simulation remains a powerful tool for predicting on-chip temperature distributions, its accuracy ultimately depends on model assumptions and boundary conditions. To bridge this gap, A design and implementation of a dedicated thermal test chip that enables direct, high-resolution experimental platform is presented. The chip, taped out on TSMC 65 nm process, integrates a 12×14 array of controllable heaters using real datapath elements and distributed temperature sensors, allowing systematic evaluation of transient and steady-state thermal responses of behavior equivariant to real chips.
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