A Formal Executable Semantics of Verilog

Meredith, Patrick; Katelman, Michael; Meseguer, José; Rosu, Grigore

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https://hdl.handle.net/2142/17079 Copy

Description

Title

A Formal Executable Semantics of Verilog

Author(s)

• Meredith, Patrick
• Katelman, Michael
• Meseguer, José
• Rosu, Grigore

Issue Date

2010-07

Keyword(s)

• Programming Languages
• Language Semantics
• Verilog
• Rewriting Logic
• rewriting logic semantics

Date of Ingest

2010-09-07T16:39:42Z

Abstract

This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous reference augmenting the prose of the official language standard, and ultimately to aid developers of Verilog-based tools; e.g., simulators, test generators, and verification tools. Our semantics applies equally well to both synthesizeable and behavioral designs and is given in a familiar, operational-style within a logic providing important additional benefits above and beyond static formalization. In particular, it is executable and searchable so that one can ask questions about how a, possibly nondeterministic, Verilog program can legally behave under the formalization. The formalization should not be seen as the final word on Verilog, but rather as a starting point and basis for community discussions on the Verilog semantics.

Type of Resource

text

Genre of Resource

Technical Report

Language

en

Permalink

http://hdl.handle.net/2142/17079

Sponsor(s)/Grant Number(s)

• CCF-0916893
• CNS-0720512
• CCF-0905584
• CCF-0448501
• NNL08AA23C

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