Novel many-core architectures for energy-efficiency

Karpuzcu, Rahmet

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https://hdl.handle.net/2142/34560 Copy

Description

Title

Novel many-core architectures for energy-efficiency

Author(s)

Karpuzcu, Rahmet

Issue Date

2012-09-18T21:25:37Z

Director of Research (if dissertation) or Advisor (if thesis)

Torrellas, Josep

Doctoral Committee Chair(s)

Torrellas, Josep

Committee Member(s)

• Hwu, Wen-Mei W.
• Patel, Sanjay J.
• Shanbhag, Naresh R.
• Kim, Nam Sung
• Wilkerson, Chris

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

• Power constraints
• Dark silicon
• Near-threshold voltage
• Many-core architectures
• Process variations
• Static random-access memory (SRAM) fault models
• Wear-Out

Abstract

Ideal CMOS device scaling relies on scaling voltages down with lithographic dimensions at every technology generation. This gives rise to faster circuits due to higher frequency and smaller silicon area for the same functionality. The dynamic power density - equivalently, dynamic power, if the chip area is fixed - stays constant. Static power density, on the other hand, increases. In early generations, however, since the share of static power was practically negligible, dynamic power density staying constant translated to total power density staying constant. This picture has changed recently. To keep the growth of the static power under control, the decrease in the threshold voltage has practically stopped. This, in turn, has prevented the supply voltage from scaling. The end effect is an increasing power density over generations, giving rise to the power wall: Processor chips can include more cores and accelerators than can be active at any given time - and the situation is getting worse. This effect, utilization wall or dark silicon, as induced by the power wall, presents a fundamental challenge that is transforming the many-core architecture landscape. This dissertation attempts to address the key implication of the power wall problem, dark silicon, in two novel and promising ways: By (1) trading off the processor service life for power and performance - the BubbleWrap many-core, and (2) exploring near-threshold voltage operation from an architectural perspective - the Polyomino many-core. The BubbleWrap many-core assumes as many cores on chip as CMOS transistor density scaling trends suggest, and exploits the resulting implicit redundancy - as not all of the cores can be powered on simultaneously - to extract maximum performance by trading off power and service life on a per-core basis. To achieve this, BubbleWrap continuously tunes the supply voltage within the course of each core's service life, leveraging any aging-induced guard-band instantaneously left, rendering one of the following regimes of operation: Minimize power at the same performance level and processor service life; attain the highest performance for the same service life while respecting the given power budget; or attain even higher performance for a shorter service life while respecting the given power budget. Effectively, BubbleWrap runs each core at a closer-to-optimal operating point by always aggressively using up all the aging-induced guard-band that the designers have included - preventing any waste of it. Another way to dim dark silicon is reducing the supply voltage to a value only slightly higher than the threshold voltage. This regime is called near-threshold voltage (NTV) computing (NTC), as opposed to conventional super-threshold voltage (STV) computing (STC). A major drawback of NTC is the higher susceptibility to parametric variations, namely the deviation of device parameters from their nominal values. To address parametric variations in present and future NTV designs, this dissertation builds on an existing model of variations at STV and develops the first architectural model of process variations at NTV. Further, using the model, this dissertation demonstrates that facilitating multiple on-chip voltage domains to handle parametric variations will not be cost effective in near-future NTV designs. With this insight, this dissertation introduces Polyomino, a simple many-core architecture which can effectively cope with variations at NTV. Polyomino eschews multiple voltage domains and relies on fine-grain frequency domains to optimize execution under variations. Thanks to Polyomino's simplicity, a variation-aware scheduler can effectively assign clusters of cores to jobs.

Graduation Semester

2012-08

Permalink

http://hdl.handle.net/2142/34560

Copyright and License Information

Copyright 2012 Rahmet Ulya Karpuzcu

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