Toward high-performance, low-power, carbon-based interconnects and transistors

Wang, Ning

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https://hdl.handle.net/2142/45604 Copy

Description

Title

Toward high-performance, low-power, carbon-based interconnects and transistors

Author(s)

Wang, Ning

Issue Date

2013-08-22T16:49:21Z

Director of Research (if dissertation) or Advisor (if thesis)

Pop, Eric

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• graphene
• carbon nanotube
• graphene nanoribbon (GNR)
• interconnect
• metal-oxide-semiconductor field-effect transistor (MOSFET)
• avalanche multiplication
• impact ionization

Abstract

As the physical limits of Moore’s law scaling are immediately apparent, industry has explored new ways of pushing technological progress. For integrated circuit applications, major limiting factors are the electrical and thermal performance of interconnects and transistors. This thesis explores two topics, the first regarding future interconnects and the second regarding nanoscale transistors, both based on low-dimensional carbon materials, which could present opportunities for extending Moore’s law. As integrated circuit performance is increasingly limited by interconnect time delays at nanoscale dimensions, graphene nanoribbons (GNRs) may serve as an effective solution. In this thesis, a comprehensive study of sub-50 nm width copper (Cu), aluminum (Al), and GNR interconnects is presented. Existing models are refined to qualitatively understand the size effect, and various interconnect geometries are simulated using finite-element solvers to study coupling capacitance. Aluminum exhibits the best performance for horizontal geometries (where the interconnect width W is greater than the height H) for 5 nm < W < 20 nm due to a superior resistivity; below 5 nm, GNRs offer better performance as coupling capacitance rapidly increases delay in Al and Cu interconnects. For vertical geometries (where H is greater than W), lower Cu resistivity yields the shortest interconnect delay until W < 8 nm; in this size regime, the width-independent GNR resistivity results in superior GNR performance over Al and Cu interconnects. For nanoscale transistors, as dimensions of traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) decrease, short channel effects degrade performance and limit further scaling. New silicon-based transistors such as the tunneling field effect transistor (TFET) and the impact ionization transistor (I-MOS) use novel carrier injection techniques to improve performance, but do not extend benefits beyond a single generation. For continued scaling, one-dimensional carbon nanotubes (CNTs) appear to be ideal, as their perfect crystalline structure and inherent cylindrical symmetry yield electrical properties superior to that of Si at similar dimensions. Thus, the second part of this document examines the possibility of CNT I-MOS transistors as a way to combine high-performance and low-power operation in highly scaled devices. If successful, the CNT I-MOS may operate at drain-source voltages of only 0.2-0.4 V for a channel length of 100 nm, which represents an order of magnitude improvement in operating voltage over existing Si-based I-MOS designs.

Graduation Semester

2013-08

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http://hdl.handle.net/2142/45604

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Copyright 2013 Ning Wang

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