Numerical simulation of fragmentation and spalling and parallelization of a spacetime finite element code

Marwah, Kartik

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https://hdl.handle.net/2142/49429 Copy

Description

Title

Numerical simulation of fragmentation and spalling and parallelization of a spacetime finite element code

Author(s)

Marwah, Kartik

Issue Date

2014-05-30T16:43:33Z

Director of Research (if dissertation) or Advisor (if thesis)

Haber, Robert B.

Department of Study

Mechanical Sci & Engineering

Discipline

Mechanical Engineering

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• discontinuous galerkin finite element
• spalling
• fragmentation
• interfacial damage
• parallel computing
• shared memory

Abstract

We present a study of the problem of spalling and fragmentation using a Space Time Discontinuous Galerkin Finite Element Method (SDGFEM) coupled with an interfacial damage model. SDGFEM offers many advantages over conventional finite element methods. These include element-wise conservation, linear computational complexity, powerful dynamic adaptive meshing, interface tracking, preservation of characteristic structure and suitability for large-scale parallel computing. The interfacial damage model and dynamic adaptive meshing allow free nucleation and propagation of cracks that are located and oriented arbitrarily in the domain without any mesh bias. This model does not alter the effective bulk properties of the material at any level of mesh refinement. Numerical examples demonstrate that the method successfully captures spall in an elastic bar and the initiation of fragmentation in a plate. We present a parallelization methodology based on shared-memory parallelism for the SDGFEM code. A patch-by-patch solution procedure, higher efficiency of the three-field SDGFEM formulation compared to the single-field formulation and linear complexity in the number of space-time elements make the SDGFEM very suitable for parallelization. Based on code profiling, the assembly and solution stages of the code are parallelized. One of the latest architectures, the Intel Many Integrated Core (MIC) architecture, available on Intel Phi Cards is explored. Sequential optimization, vectorization and OpenMP multi-threading lead to good speedups. Some initial results obtained using the MIC architecture seem promising and complete parallelization on the MIC architecture is planned as an extension of this work.

Graduation Semester

2014-05

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http://hdl.handle.net/2142/49429

Copyright and License Information

Copyright 2014 Kartik Marwah

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