Single Core Equivalent Virtual Machines for Hard Real—Time Computing on Multicore Processors
Author(s)
Sha, Lui
Caccamo, Marco
Mancuso, Renato
Kim, Jung-Eun
Yoon, Man-Ki
Pellizzoni, Rodolfo
Yun, Heechul
Kegley, Russel
Perlman, Dennis
Arundale, Greg
Bradford, Richard
Issue Date
2014-11-05
Keyword(s)
Multi-Core
Real-Time
FAA
Certification
Certifiable
Performance Isolation
Single Core
Single Core Equivalence
UAVs
Avionics
Automotive
Date of Ingest
2014-11-05T20:25:24Z
Abstract
The benefits of adopting emerging multicore processors include reductions in space, weight, power, and cooling, while increasing CPU bandwidth per processor. However, the existing real-time system engineering process is based on the constant worst case execution time (WCET) assumption, which states that the measured worst case execution time of a software task when executed alone is the same as when that task is running together with other tasks. While this assumption is correct for single-core chips, it is NOT true for multicore chips. As it is now, the interference between cores can cause delay spikes as high as 600% in industry benchmarks. This paper reviews a technology package, namely Single Core Equivalence (SCE), that restores the constant WCET assumption so that engineers can treat each core in a multicore chip as if it were a single core chip. This is significant since FAA permits the use of only one core in a multicore chip due to inter-core interferences.
Type of Resource
text
dataset / spreadsheet
image
Genre of Resource
Technical Report
Language
en
Permalink
http://hdl.handle.net/2142/55672
Sponsor(s)/Grant Number(s)
CNS-1302563; CNS-1219064; ONR N00014-12-1-0046; Lockheed Martin 2009-00524; Rockwell Collins RPS#645038
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