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New Techniques for Logic Built -in Self -Test
Doctoral Committee Chair(s)
Patel, Janak H.
Department of Study
Degree Granting Institution
University of Illinois at Urbana-Champaign
The dissertation investigates new techniques for logic built-in self-test (BIST) in VLSI chip testing. The main purpose of these techniques is to improve fault coverage for logic BIST with minimal performance penalty and hardware overhead. One technique is the method of constrained scan cells. It overcomes the timing penalty of control points by enhancing controllability of CUT through scan path instead of functional path. By combining constrained scan cells with observation points in BIST implementation, BIST coverage comparable to test point insertion is achieved. The hardware overhead is maintained at a low level. Another technique is weighted pattern testing with complementary weights. Two implementations are proposed for the method. One is scan chain segmentation; the other is decoder logic based implementation. In scan chain segmentation, complementary weights are obtained by using inverters to partition scan chains into multiple segments. Successive segments assume complementary weights when highly weighted patterns are shifted in. The decoder logic based implementation uses the outputs from the decoder logic to modulate the weight feeding into the scan chain. The synthesis of the decoder logic utilizes the complementary weight sets computed from deterministic test set. Multiple complementary weight pairs are used to further enhance the performance of complementary weights. It is shown that the method of complementary weights is able to achieve very high coverage with very low hardware overhead. Like many other weighted patterns based techniques, no test point is used to interfere with the core design. Further analysis of complementary weight sets shows its potential for programmable implementation.