Low-Spurious Analog-to-Digital Conversion Using Multi-Stage Code-Error Calibration

Kwak, Sung Ung

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https://hdl.handle.net/2142/81213 Copy

Description

Title

Low-Spurious Analog-to-Digital Conversion Using Multi-Stage Code-Error Calibration

Author(s)

Kwak, Sung Ung

Issue Date

1997

Doctoral Committee Chair(s)

Song, Bang-Sup

Department of Study

Electrical Engineering

Discipline

Electrical Engineering

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

Engineering, Electronics and Electrical

Language

eng

Abstract

This thesis presents a 5-5-5-6b pipelined ADC architecture that alleviates the requirements for initial capacitor matching and residue amplifier settling accuracy. The two 5-bit MSB stages are digitally calibrated to implement a 15-bit, 5 Msample/s low-spurious ADC using 1.4 $\mu$m CMOS. A skip-and-fill algorithm with non-linear interpolation also opens up the possibility of calibrating ADCs in the background synchronously with their normal operations. Interpolation results for the background calibration are compared with the foreground calibration results. The prototype ADC exhibits a DNL of +0.75/$-$0.6 LSB, an INL of +1.77/$-$1.58 LSB, and all spurious components are suppressed to below $-$93 dB when sampled at 5 MHz. The chip occupies an active area of 27 mm$\sp2,$ and the analog part consumes 60 mW at 5 V. Memory and arithmetic units for calibration are supplied externally in testing.

Graduation Semester

1997

Type of Resource

text

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http://hdl.handle.net/2142/81213

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