Architectural Techniques to Mitigate the Effect of Spatial and Temporal Variations in Processors
Tiwari, Abhishek
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https://hdl.handle.net/2142/81837
Description
Title
Architectural Techniques to Mitigate the Effect of Spatial and Temporal Variations in Processors
Author(s)
Tiwari, Abhishek
Issue Date
2008
Doctoral Committee Chair(s)
Torrellas, Josep
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Computer Science
Language
eng
Abstract
To address this problem, we show how to hide the effects of aging and slow it down. Our framework is called Facelift. It hides aging through aging-driven application scheduling. It slows down aging by applying voltage changes at key times---it uses a non-linear optimization algorithm to carefully balance the impact on the aging rate and on the critical path delays. Moreover, it can gainfully configure the chip for a short lifetime. We can take a multicore with a 7-year lifetime and, by hiding and slowing down aging, enable it to cycle, on average, at a 14--15% higher frequency. Alternatively, we can design a multicore for a 5 to 7-month lifetime and use it for 7 years.
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