Power Estimation and Minimization of Digital Signal Processing Systems
Ramprasad, Sumant
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https://hdl.handle.net/2142/81947
Description
Title
Power Estimation and Minimization of Digital Signal Processing Systems
Author(s)
Ramprasad, Sumant
Issue Date
1999
Doctoral Committee Chair(s)
Naresh Shanbhag
Ibrahim Hajj
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
We have so far focussed on power dissipation in static CMOS circuits. Dynamic logic circuits are used in high-performance circuits due to their speed and area advantage over static CMOS circuits. In this thesis, we also present an optimization technique, termed clock-generating (CG) domino, for dual-output domino logic that reduces area, dock load, and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output.
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