University of Illinois Urbana-Champaign

Evaluating the performance of high-level synthesis tools across languages: A case study on convolutional neural network on FPGA

Kim, Dae Hee

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https://hdl.handle.net/2142/91544

Description

Title
Evaluating the performance of high-level synthesis tools across languages: A case study on convolutional neural network on FPGA
Author(s)
Kim, Dae Hee
Contributor(s)
Chen, Deming
Issue Date
2016-05
Keyword(s)
  • convolutional neural networks
  • field-programmable gate arrays (FPGAs)
  • high-level synthesis
Abstract
As Convolutional Neural Networks (CNNs) become popular for object recognition, testing performance of CNNs on Field Programmable Gate Array (FPGA) is also an interesting topic. By having high performance of CNN on FPGA, we are able to have an object recognizing device anywhere, enabling such technologies as automated cars. In order to implement CNN on FPGA, one has to program it with low level languages such as Verilog or VHDL. However, it would be much simpler if one can code CNN with a high level language like C, C++, or Matlab and convert it to Verilog using a High Level Synthesis tool. Since there are many languages, it is very useful to know the performance difference of CNN if it is implemented with different languages. My research focuses on comparing C and Matlab code. CNN is implemented with both C and Matlab and they are converted to VHDL. During the process, we realized that it is much easier for C code to go through high level synthesis tool than Matlab. Therefore, in terms of letting CNN go through high level synthesis, C code would be preferred. However, comparing performance difference on FPGA still needs to be done.
Type of Resource
text
Language
en
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http://hdl.handle.net/2142/91544

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