Design of a clock and data recovery circuit in 65 nm technology

Ren, Yi

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https://hdl.handle.net/2142/92964 Copy

Description

Title

Design of a clock and data recovery circuit in 65 nm technology

Author(s)

Ren, Yi

Issue Date

2016-07-19

Director of Research (if dissertation) or Advisor (if thesis)

Schutt-Ainé, José E.

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

Clock and data recovery (CDR)

Abstract

As semiconductor fabrication technology develops, the demand for higher transmission data rates constantly increases; thus there is an urgent need for a power-efficient, robust and broad bandwidth chip-to-chip communication method. A lot of work has been done to address this issue as researchers strive for more integrated inter-IC communication technology with CMOS. A high-speed serial link (HSSL) can help meet this goal. The clock and data recovery circuit (CDR) is a critical component of the HSSL. CDR is built on the receiver end of the link after proper equalization. Its purpose is to extract clock signal which is not transmitted from the driver end and to use the extracted clock signal to sample the incoming data stream with optimal timing. In this thesis, the working mechanism of the CDR is described. A CDR consists of a phase detector, a charge pump, a loop filter and a voltage-controlled oscillator. This thesis includes an overview of all the building blocks of a PLL-based CDR, derivation of the mathematical formulations of the negative feedback loop, and a report on closed loop behavioral modeling of the entire CDR and implemented CDR building blocks at transistor level with TSMC 65 nm technology PDK with a 6.4 Gbps data rate. Also, this thesis provides a detailed noise analysis of the CDR. Lastly, some future work and possible design improvements are proposed.

Graduation Semester

2016-08

Type of Resource

text

Permalink

http://hdl.handle.net/2142/92964

Copyright and License Information

Copyright 2016 Yi Ren

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