University of Illinois Urbana-Champaign

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Showing 1–30 of 153 items
Thumbnail for Timing and Area Optimization for Standard-Cell VLSI Circuit Design
Timing and Area Optimization for Standard-Cell VLSI Circuit Design
Chuang, Weitong; Sapatnekar, Sachin S.; Hajj, Ibrahim N.

Thumbnail for Parallel-Concurrent Versus Concurrent Fault Simulation
Parallel-Concurrent Versus Concurrent Fault Simulation
Saab, Daniel Georges; Rahmeh, Joseph T.; Hajj, Ibrahim N.

Thumbnail for Logic Design Error Diagnosis and Correction
Logic Design Error Diagnosis and Correction
Chung, Pi-Yu; Wang, Yi-Min; Hajj, Ibrahim N.