University of Illinois Urbana-Champaign

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Showing 901–930 of 27,406 items
Thumbnail for Timing Verification and Synthesis of Circuits for Delay Fault Testability
Timing Verification and Synthesis of Circuits for Delay Fault Testability
Roy, Kaushik

Thumbnail for Hierarchical Approaches to VLSI Circuit Layout
Hierarchical Approaches to VLSI Circuit Layout
Sarrafzadeh, Majid

Thumbnail for A Parallel Algorithm for Multi-Level Logic Synthesis Using the Transduction Method
A Parallel Algorithm for Multi-Level Logic Synthesis Using the Transduction Method
Lim, Chieng-Fai

Thumbnail for Low cycle fatigue properties of ausformed steel
Low cycle fatigue properties of ausformed steel
Matheny, J.E., Jr.

Thumbnail for iSITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI Circuits
iSITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI Circuits
Gee, Perry

Thumbnail for Switch-Level Timing Simulation of MOS VLSI Circuits
Switch-Level Timing Simulation of MOS VLSI Circuits
Rao, Vasant Bangalore

Thumbnail for Parallel Algorithms for Sequential Circuit Fault Simulation and Test Generation
Parallel Algorithms for Sequential Circuit Fault Simulation and Test Generation
Krishnaswamy, Dilip

Thumbnail for Investigation of the impacts of deploying reactors fueled by high-assay low enriched uranium
Investigation of the impacts of deploying reactors fueled by high-assay low enriched uranium
Bachmann, Amanda M • 2024

Thumbnail for Enhancement of the Illinois Scan Architecture for Multiple Scan Inputs and Transition Faults
Enhancement of the Illinois Scan Architecture for Multiple Scan Inputs and Transition Faults
Shah, Mihir Atul

Thumbnail for Analysis of Failures in Windows NT Systems
Analysis of Failures in Windows NT Systems
Kalyanakrishnan, Mahesh Chittur

Thumbnail for Parallel Processing Techniques for the Simulation of MOS VLSI Circuits Using Waveform Relaxation
Parallel Processing Techniques for the Simulation of MOS VLSI Circuits Using Waveform Relaxation
Smart, David William

Thumbnail for The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms
The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms
Rogers, William Arthur

Thumbnail for Estimating fatigue crack initiation and propagation lives in notched plates under variable loading histories
Estimating fatigue crack initiation and propagation lives in notched plates under variable loading histories
Socie, Darrell F.

Thumbnail for Worst Case Voltage Drops in Power and Ground Buses of CMOS VLSI Circuits
Worst Case Voltage Drops in Power and Ground Buses of CMOS VLSI Circuits
Kriplani, Harish

Thumbnail for Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers
Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers
Tejayadi, Ongky

Thumbnail for Design, Analysis and Reconfiguration of Defect-Tolerant VLSI and Parallel Processor Arrays
Design, Analysis and Reconfiguration of Defect-Tolerant VLSI and Parallel Processor Arrays
Shi, Weiping

Thumbnail for Statistical Design of MOS VLSI Circuits with Designed Experiments
Statistical Design of MOS VLSI Circuits with Designed Experiments
Yu, Tat-Kwan Edgar

Thumbnail for Performance Aspects of Computers with Graphical User Interfaces
Performance Aspects of Computers with Graphical User Interfaces
Gupta, Aloke

Thumbnail for Delay Fault Testing for Enhanced Full Scan Based Circuits
Delay Fault Testing for Enhanced Full Scan Based Circuits
Sharma, Manish

Thumbnail for Statistical Error Compensation for Robust Digital Signal Processing and Machine Learning
Statistical Error Compensation for Robust Digital Signal Processing and Machine Learning
Kim, Eric Park

Thumbnail for Software and Hardware Techniques for Masking Security Vulnerabilities
Software and Hardware Techniques for Masking Security Vulnerabilities
Xu, Jun

Thumbnail for Water table use in studies of pressure waves in fluid power systems
Water table use in studies of pressure waves in fluid power systems
Holt, C. F.; Labus, T. J.; Robertson, J. M.

Thumbnail for Parallel Algorithms for Test Generation and Fault Simulation
Parallel Algorithms for Test Generation and Fault Simulation
Patil, Srinivas

Thumbnail for A Convex Programming Approach to Problems in VLSI Design
A Convex Programming Approach to Problems in VLSI Design
Sapatnekar, Sachin Suresh

Thumbnail for Taking control: Identifying motivations for migrating library digital asset management systems
Taking control: Identifying motivations for migrating library digital asset management systems
Stein, Ayla; Thompson, Santi

Thumbnail for Evaluation of a Design for Concurrent Error Detection and Testability in Large Storage/Logic Arrays
Evaluation of a Design for Concurrent Error Detection and Testability in Large Storage/Logic Arrays
Maciukenas, Thomas Brian

Library Trends 45 (3) Winter 1997: Resource Sharing in a Changing Environment
Library Trends 45 (3) Winter 1997: Resource Sharing in a Changing Environment. Edited by Chandra Prabha and Gay N. Dannelly.
Thumbnail for Development of a Long-term, Multimetric Structural Health Monitoring System for a Historic Steel Truss Swing Bridge
Development of a Long-term, Multimetric Structural Health Monitoring System for a Historic Steel Truss Swing Bridge
Giles, Ryan K.; Spencer, Billie F., Jr.

Thumbnail for Functional Models for MOS VLSI Circuits
Functional Models for MOS VLSI Circuits
Wehbeh, Jalal Anis

Thumbnail for Parallel Processing for VLSI Simulation
Parallel Processing for VLSI Simulation
Mueller-Thuns, Robert Bernard